Field
This disclosure relates generally to integrated circuit device packaging, and more specifically, to packaging an integrated circuit device with stress buffer.
Related Art
Today, many integrated circuit devices are packaged in low cost packaging which generally includes a semiconductor die encapsulated in a plastic encapsulant. As integrated circuit devices become more and more sophisticated, some circuitry can be sensitive to thermo-mechanical stresses commonly associated with low cost packaging. For example, sensitive analog circuitry may require voltage tolerances such as +/−0.1 mV but package stress can cause the sensitive circuitry to exceed required voltage tolerance with performance such as +/−5 mV. One way to reduce stress effects on the sensitive circuitry is to add steps to the manufacturing process such as at wafer level, applying a patterned dielectric material directly above the sensitive circuitry while in wafer form before encapsulating the semiconductor die with an encapsulant. However, additional steps added to the manufacturing process can significantly impact the overall integrated circuit device complexity and cost. What is needed is a more cost effective approach to reduce stress in packaged integrated circuit devices.